The present invention relates to semiconductor memory devices and specifically, to flash memory devices.
Flash memory devices operable with read, program, and erase operations usually include page buffer circuits. By the page buffer circuits, data of large volume are programmed into the flash memory device in the unit of page for a short time or read out from the flash memory device in the unit of page. FIG. 1 is a circuit diagram showing a page buffer circuit and Y-gate circuit of a conventional flash memory device. Referring to FIG. 1, the page buffer circuits P1˜PK (K is an integer) are connected to pairs of bitlines BLe1/BLo1˜BLeK/BLoK, each corresponding thereto. The page buffer circuits P1˜PK are also connected to Y-gate circuits G1˜GK (K is an integer), each corresponding thereto. Each of the page buffer circuits P1˜PK includes NMOS transistors NM1˜NM6, a PMOS transistor PM1, and a latch circuit LA. The NMOS transistors NM1 and NM2 are turned on or off in response each to bitline selection signals, one of BSLe˜BSLeK and one of BSLo1˜BSLoK. The NMOS transistors NM1 and NM2 are turned on to connect the bitlines, one of BLe1˜BLeK and one of BLo1˜BLoK, each to a sensing node S1˜SK. The PMOS transistor PM1 is turned on or off in response to a precharge signal, one of PRCHb1˜PRCHbK. The NMOS transistor NM3 is turned on or off in response to a program control signal, one of PGM1˜PGMK. When the NMOS transistor NM3 is turned on, a data bit (not shown) received from the latch circuit LA is transferred to a bitline connected to the sensing node (one of S1˜SK), one of BLe1˜BLeK or one of BLo1˜BLoK. The NMOS transistor NM4 is turned on or off in response to the sensing node, one of S1˜SK, while the NMOS transistor NM5 is turned on or off in response to a latch control signal, one of LCH1˜LCHK. The NMOS transistor NM6 initializes the latch circuit LA in response to a reset control signal RST. The Y-gate circuits G1˜GK transfer read data, which are received from their corresponding page buffer circuits P1˜PK, an input/output line IOL in response to the control signals YS1˜YSK, respectively, or transfer program data (not shown) to the page buffer circuits P1˜PK from the input/output line IOL, respectively.
As aforementioned, as the conventional flash memory device needs one Y-gate circuit for one pair of bitlines, an increase in the number of bitlines causes an increase in the number of Y-gate circuits. As a result, it increases the size occupied by the Y-gate circuits, enlarging the size of the flash memory device. Further, if the number of the Y-gate circuits increases, it is required for a Y-decoder to have more control signals to control operations of the increased Y-gate circuits, as well as increasing the number of lines to supply the control signals.